The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design, and nanometer technology have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs, but also increases the complexity of processing and manufacturing ICs and castes challenges on both fabrication and design.
For the next technological generations of integrated circuits, the traditional challenges faced such as profile control, etch selectivity, critical dimensions, uniformity, defects, etc. become more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. With shrinking geometries as technology nodes advance to 45 nm and beyond, and with adoption of lower k dielectrics and thinner barriers to minimize device RC (the time constant, R: resistance, C: capacitance) delay, there is a need for advanced patterning schemes to obtain reliable, high yield and low-resistance interconnects. Since it is difficult to make the photoresist (PR) films used in semiconductor fabrication thinner to etch sub-45 nm devices, a metal or ceramic hard mask film, such as titanium nitride (“TiN”), came to be widely used, instead of the conventional SiO2 hard mask, for its hardness and different etching selectivity to oxide films of low k materials during Cu dual damascene patterning. A TiN hard mask further allows partial via etch approach and eliminates ultra-low K damage caused by the resist ash strip process.
Despite various advantages with the TiN hard mask, a problem has been noted. When a TiN hard mask is formed by a conventional PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition), it has been observed that, after patterning narrow trenches for interconnects, and especially after deposition of an anti-diffusion barrier film upon the trench sidewalls that have a TiN hard mask formed at its top, the trench sidewalls suffer from high stress, and end up with profile distortions, which causes shrinkage of the trench openings or via openings. When the trench openings shrink, interconnect metals such as copper cannot fully fill the trenches, creating so-called Cu voids in the interconnects or vias, impairing the interconnect reliability and via RC yield. The stress causing such distortions may be attributed to the highly compressive residual stress in the TiN hard mask, which originates partly from the TiFx compounds which settle on the trench sidewalls, and partly from the deposited anti-diffusion barrier film.
Therefore, for improving the interconnect reliability and via RC yield that suffer from the copper void problem caused by the trench/via opening shrinkage, there is a need to provide a method for forming a metallic or ceramic hard mask, such as a TiN hard mask, in fabricating semiconductor device, especially in forming metallic interconnects, in such a way to control internal stress of the hard mask to counter-balance the residual stress that causes the profile distortion.